1. Field of the Invention
The present invention relates to the art of power supplies, and in particular to an analog multiplier-divider for a power factor correction (PFC) circuit.
2. Description of the Prior Art
There are many uses for analog multiplier-dividers in modern electronics. Multiplier-dividers produce an output signal that is proportional to a ratio of two or more input signals. The input and output signals can either be voltages or currents.
One common use of multiplier-dividers is in power factor correction (PFC) circuits. PFC circuits commonly use multiplier-dividers to generate a control signal based on the input current, the feedback signal, and the input voltage. FIG. 1 demonstrates the use of an analog multiplier-divider in a PFC circuit.
There are many known ways of constructing analog multiplier-dividers, such as logarithmic amplifiers and antilog amplifiers. The implementation of a logarithmic amplifier normally uses the p-n junction volt-ampere characteristic; it is given byID=I0×[exp(VD/ηVT)−1]  (1)
where I0 is the reverse saturation current; VD is the forward bias voltage; η is the constant; VT=T/11,600 and T is the temperature ° K. Since the output current ID is the exponential function of the forward bias voltage VD, the linear operating region is small. The book “Analog Integrated Circuit Design” by David A. Johns and Ken Martin (1997, pg. 366–367) teaches a known analog multiplier-divider. This particular multiplier-divider is also referred to as a four-quadrant multiplier. It is shown in FIG. 2.
The prior-art analog multiplier-divider shown in FIG. 2 supplies an output current with an amplitude that is proportional to the product of a first input current and a current ratio. The current ratio is equal to the amplitude of a second input current divided by the amplitude of a bias current. The prior-art multiplier-divider shown in FIG. 2 is built using bipolar transistor devices.
Many other known prior-art multiplier-dividers exist that are based on the principles of the prior-art multiplier-divider shown in FIG. 2. They all share the same disadvantages, to the extent that they are built using bipolar transistor devices.
One disadvantage of the prior-art multiplier-divider shown in FIG. 2 is that it is a bipolar device. For many present-day applications, such as PFC circuits, integrated circuits manufactured using a bipolar process are not suitable, because their die-size are too large and the cost is too high.
Another disadvantage of the prior-art multiplier-divider shown in FIG. 2 is that the output of the circuit varies significantly with temperature. The characteristic equations of bipolar transistors have high temperature coefficients. Thus, the output of the circuit is highly susceptible to temperature changes.
Another disadvantage of the prior-art multiplier-divider shown in FIG. 2 is high power consumption. The prior-art multiplier-divider requires a constant non-zero biasing current to bias bipolar transistors in linear mode. This results in significant power consumption.
Another disadvantage of the prior-art multiplier-divider shown in FIG. 2 is poor noise immunity. The prior-art multiplier-divider uses high-gain bipolar transistor devices. With such devices, even relatively small input signal distortion can result in significant output signal distortion.
Another disadvantage of the prior-art multiplier-divider shown in FIG. 2 is that it has a narrow input range, limited to the linear operating region of bipolar transistors. Outside of this narrow input range, the multiplier-divider shown in FIG. 2 is highly susceptible to distortion.
Therefore, there is a need for an improved analog multiplier-divider. In particular, there is a need for an improved analog multiplier-divider that has a smaller die size while being suitable for a wider range of operating temperatures.